1. Field of the Invention
The present invention relates generally to the field of nonvolatile memory devices. More particularly, the present invention relates to a single-poly nonvolatile memory (NVM) cell structure with improved data retention.
2. Description of the Prior Art
Non-volatile memory (NVM) is a type of memory that retains information it stores even when no power is supplied to memory blocks thereof. Some examples include magnetic devices, optical discs, flash memory, and other semiconductor-based memory topologies.
For example, U.S. Pat. No. 6,678,190 discloses a single-poly NVM having two serially connected PMOS transistors wherein the control gate is omitted in the structure for layout as the bias is not necessary to apply to the floating gate during the programming mode. A first PMOS transistor acts as a select transistor. A second PMOS transistor is connected to the first PMOS transistor. A gate of the second PMOS transistor serves as a floating gate. The floating gate is selectively programmed or erased to store predetermined charges.
It is desirable that the charge stored on a floating gate is retained for as long as possible, thereby increasing the data retention time of the NVM.